IBM Telum
| General information | |
|---|---|
| Launched | 2021 |
| Designed by | IBM |
| Common manufacturer | |
| Performance | |
| Max. CPU clock rate | 5.2 GHz |
| Physical specifications | |
| Cores |
|
| Cache | |
| L2 cache | 32 MB per core |
| Architecture and classification | |
| Technology node | 7 nm |
| Instruction set | z/Architecture |
| History | |
| Predecessor | z15 |
| Successor | Telum II |
Telum is a microprocessor made by IBM for the IBM z16 series mainframe computers.[2][3] The processor was announced at the Hot Chips 2021 conference on 23 August 2021.[2] Telum is IBM's first processor that contains on-chip acceleration for artificial intelligence inferencing while a transaction is taking place.[4][5]
Description
The chip contains 8 processor cores with a deep superscalar out-of-order pipeline, running with more than 5 GHz clock frequency which is optimized for the demands of heterogenous enterprise-class workloads (e.g: finance, security sensitive applications, applications requiring extreme reliability). The cache and chip-interconnection infrastructure provides 32 MB cache per core and can scale to 32 Telum chips.[6][3][7] The cache design has been described as "revolutionary" in 2021,[6] by creating a system where the L2 cache of one core can be used as virtual L3 and L4 caches for another core.[3][1] The Telum processor can either be water cooled or air cooled, but water cooling is required for running more than a few Telum processors in a single IBM compute drawer.[8][9] Unlike other processors, the IBM Telum does not thermal throttle by reducing clock speed; instead it inserts sleep state instructions.[8][9]
Telum adds a new 16-bit floating point format (NNP-Data-Type-1 Format) and several new instructions.[10] The Neural Network Processing Assists (NNPA)[11] instruction performs a variety of tensor instructions useful for neural networks.[a]
Telum II adds new functions to NNPA.[12]
See also
Manuals
- z-14
- z/Architecture Principles of Operation (PDF) (Fourteenth ed.). IBM. May 2022. pp. 26-61 – 26-96. SA22-7832-13. Retrieved March 31, 2025.
- z-15
- z/Architecture Principles of Operation (PDF) (Fifteenth ed.). IBM. April 2025. SA22-7832-14. Retrieved March 31, 2025.
Notes
- ^ The NNPA instruction does not specify its operands; rather, General Register 0 contains a function code (FC) and General Register 1 contains the address of a parameter block. Depending on the function, the parameter block may contain up to 4 tensor descriptors.
References
- ^ a b Hudson, Andrew (24 July 2023). "The IBM mainframe: How it runs and why it survives". Ars Technica. Retrieved 25 July 2023.
- ^ a b Moorhead, Patrick (23 August 2021). "IBM Telum- A New Chapter In Vertically Integrated Chip Technology". Forbes. Retrieved 12 May 2023.
- ^ a b c Johnson, Dexter (29 April 2022). "IBM's New Telum Chip Reboots the Mainframe". IEEE Spectrum. Retrieved 5 May 2022.
- ^ Combs, Veronica (24 August 2021). "IBM's new Telum Processor is the company's first with an on-chip AI accelerator". TechRepublic. Archived from the original on 2023-03-22. Retrieved 27 August 2021.
- ^ Sperling, Ed (26 August 2021). "New Approaches For Processor Architectures". Semiconductor Engineering. Retrieved 25 July 2023.
- ^ a b Cutress, Ian (2 September 2021). "Did IBM Just Preview The Future of Caches?". Anandtech. Archived from the original on September 2, 2021. Retrieved 5 May 2022.
- ^ Sebastian, Linus (5 April 2022). "I Tried to Break a Million Dollar Computer - IBM Z16 Facility Tour!" (video). YouTube. Linus Media Group. Retrieved 5 May 2022.
- ^ a b IBM z16 Technical Introduction (PDF) (Second ed.). IBM. April 2023. SG24-8950-01.
- ^ a b Why Do Mainframes Still Exist? What's Inside One? 40TB, 200+ Cores, AI, and more!, 28 October 2023, retrieved 2024-01-11
- ^ PoOps14, pp. xxxiii–xxxiv, Summary of Changes in Fourteenth Edition
"The fourteenth edition of this publication differs from the previous edition principally by containing the definitions of the following facilities:- BEAR-enhancement facility
- Enhanced-sort facility
- Mapped-I/O-addressing facility [PCI ONLY]
- Neural-network-processing-assist facility
- Processor-activity-instrumentation facility
- Processor-activity-instrumentation extension 1
- Reset-DAT-protection facility
- Storage-key-removal facility
- Vector-packed-decimal-enhancement facility"
- ^ PoOps14, pp. 26-61–26-96, NEURAL NETWORK PROCESSING ASSIST.
- ^ PoOps15, pp. xxxiii–xxxiv, Summary of Changes in Fifteenth Edition.